A buck converter is a step-down DC to DC voltage converter that converts a higher DC voltage input to a lower and regulated DC voltage output. A buck converter's design may be similar to that of a step-up boost converter, and like some boost converter circuitry it is a switched-mode power supply that incorporates two solid state switches (i.e., a transistor and a diode or two transistors), an inductor and a capacitor to convert an input DC voltage to a regulated output DC voltage.
The simplest way to reduce a DC voltage is to use a voltage divider circuit. The problem with voltage divider circuitry is that they waste energy since they operate by bleeding off excess power as heat through a resistor. Furthermore, with a basic voltage divider circuit the output voltage is not regulated. When a voltage is not regulated it means that the output voltage varies with the input voltage. A buck converter, on the other hand, is a remarkably efficient and self regulating circuit making it useful for converting 12 to 50 volts DC down to, for example, a regulated lower voltage such as 0.5 to 10 volts DC, which may be needed for various circuits and sub-circuits within an electronic device.
Referring now to FIG. 1 wherein a general prior art buck converter circuit is depicted we see a DC voltage input 10 of the buck converter and the DC stepped-down voltage output 12 of the buck converter. Between the input 10 and the output 12 of the buck converter is a high-side switching transistor 14 and a low-side switching transistor 16. In some buck converters the low-side switching transistor 16 is replaced with a diode (not specifically shown). The high and low-side switches 14 and 16 may be MOSFETS, JFETS or BJT transistors or reasonable derivations thereof. A pulse width modulator 18 provides a modulated signal 20 to the high-side switch 14. An inverter 22 may be provided to provide an inverted DH signal or DL signal 24 to the low-side switch 16. In some embodiments, an inverter is not used, but is instead provided within the circuitry of the pulse width modulator and a DH signal 20 and a DL signal 24 are provided as separate outputs from the pulse width modulator 18. An exemplary DH signal 20 is shown as signal 21 having a duty cycle 26 wherein a first part of the duty cycle is high 28 and a second part of the duty cycle is low 30.
A buck converter typically has an error amplifier 32 that senses a feedback voltage VFB 34, which is the output voltage 12 attenuated by a resistor voltage dividing circuit comprising resistors R1 36 and R2 38. The feedback voltage 34 is provided to one of the inputs of the error amplifier 32 wherein the feedback voltage 34 is compared with a reference voltage (VREF) 40. A voltage reference is generally created by some type of voltage reference circuit 42, which may provide a constant voltage reference 44 or a soft start voltage reference 46, which starts at 0 volts and then rises to a constant or fixed voltage much like the fixed voltage reference 44. The error amplifier 32 compares the feedback voltage 34 with the voltage reference 40 and will try to drive the feedback voltage to equal the voltage reference thereby driving or regulating the voltage output 12 to be at some predetermined output voltage.
In other words, the error amplifier 32, which is typically found in a buck converter, senses the voltage of the VOUT node 12 attenuated by the resistor voltage divider network comprised of resistors R1 36 and R2 38 at the voltage feedback node 34. The feedback voltage 34 is then compared with a voltage reference 40 in the error amplifier 32 such that the error amplifier produces a control signal 48 that is used to set the duty cycle of the pulse switching of the high-side transistor 14 and the low-side switch or transistor 16 via the pulse width modulation circuit 18. The continuous control signal 48 coming out of the error amplifier 32 is transformed into the DH signal 20, which is a pulse width modulated signal provided by the pulse width modulation circuit 18. The DH signal is used to drive the high-side transistor 14 and, if a low-side transistor is used, to drive the low-side transistor 16 as well. In some embodiments the low-side transistor 16 is not used, but instead a diode or a rectifier is used in its place.
The switching of the high and low sides of the switching circuitry 14 and 16 operates at a higher bandwidth or frequency than the bandwidth of the feedback loop provided by the feedback voltage 34. A duty cycle of the switching creates a chopped pulse width modulated signal at the switching node 50. A possible modulated signal 52 that may be present at the switching node is shown. When the switching signal DH 20 is high, it turns the high-side switch 14 on and drives the voltage at the switching node 50 high to be about equal to the input voltage found at VIN 10. When the DH signal 20 goes low then the DL signal 24 is high, which turns on the low-side switch 16, which will pull the switching node 50 (also known as the LX node) to ground. The resulting chopped modulated signal 52 found at the switching node 50 proceeds through the inductor 54 to the output voltage 12. The inductor 54 smoothes out the chopped voltage of the pulse width modulated signal 52. Smoothing of the modulated signal 52 at the switching node 50 by the inductor 54 and capacitor 56 creates a nearly constant DC voltage output at the voltage output node 12. Generally the value of the output voltage at the voltage output 12 is equal to the average value of the modulated signal 52 found at the switching node 50. Furthermore, the average value of the modulated signal 52 at the switching node 50 is roughly equal to the duty cycle of the switching times the input voltage (assuming that when the low-side switch 16 is turned on it is pulling the switching node voltage to ground). For example, if the duty cycle is 20% (i.e., 20% on, 80% off) then the output voltage at VOUT 12 will be approximately 20% of the input voltage found at VIN 10.
The feedback voltage 34, which is an attenuated voltage of the output voltage found at VOUT 12, is then fed back to the error amplifier 32 and compared with the voltage reference voltage 40. The error amplifier senses the difference between the voltage reference voltage 40 and the feedback voltage 34 and adjusts its output signal 48 to change the pulse width modulated signal being produced by the pulse width modulator 18 and, so the buck regulator uses feedback to regulate its stepped down output voltage.
Still referring to FIG. 1, it is important to understand drawbacks of a step-down or buck converter that operates similarly to the buck converter circuitry of FIG. 1. In particular, the output voltage of a prior art buck converter can cause damage to the circuitry that is being powered. For example, if at start up, the output voltage found at the voltage output 12 is 0 volts and the voltage reference 40 being provided to the error amplifier 32 is a steady state voltage reference voltage 44, then the error signal or modulation control signal 48 that is output from the error amplifier 32 will push the pulse width modulator 18 to produce a very large duty cycle modulation signal to the switching transistors 14 and 16. A very large duty cycle means that the high-side switching transistor 14 will be held “on” for a long period of time basically creating an enormous amount of current flowing through the switching node 50 and the inductor 54. The current indicated by iL 60 could be damaging to the switching transistor 14 and/or the inductor 54. Furthermore, with such a large duty cycle being provided by the DH modulation signal 20 (i.e., the high part of the duty cycle signal 28 would extend for the majority of the duty cycle signals cycle length 26. The large duty cycle may produce an excessive output voltage at VOUT 12 that causes the feedback voltage 34 to overshoot the reference voltage 44, which is necessary to balance or provide a correct voltage output at VOUT 12, forcing the error amplifier 32 to swing the voltage error signal 48, provided to the pulse width modulator circuitry 18, the other direction such that the duty cycle 28 would be quite short and thus the high-side switching transistor 14 would be turned off and the low-side switching transistor 16 (or low-side diode) would be turned on pulling the switching node 50 to ground. This “ringing” of the output voltage 12 would continue to occur until the voltage feedback 34 and voltage reference 40 voltages were smoothed out by the feedback loop of the error amplifier 32 in conjunction with the pulse width modulator 18. One major problem of this type of turning on or initializing a buck converter is that the circuitry (not specifically shown) that receives the voltage output 12 is generally low voltage and sensitive circuitry that may not necessarily be able to handle an over voltage at the VOUT node 12. A high output voltage 12 that is higher than expected by the circuitry being driven by the output voltage 12 of the buck converter, may damage the sensitive circuitry receiving power from the buck converter.
Another problem with the design of the prior art buck converter found in FIG. 1 occurs when the output voltage at the VOUT 12 of the buck converter is floating at a non-zero voltage when the buck converter is turned on or initialized. For example, if for some reason the output voltage at VOUT 12 is at or near about half the output voltage that the buck converter is to produce, then the V feedback voltage 34 will be initially much smaller than the voltage reference voltage 40 at the input of the error amplifier 32. This situation will once again cause the pulse width modulator 18 to produce a modulation signal 20 having a very large duty cycle 28 that forces the high-side switching transistor 14 to be on for long periods of time thereby, like the previous example, over shooting the desired output voltage at VOUT 12 initially at start up until the feedback voltage 34, in conjunction with the error amplifier and the other feedback circuitry 32, 18 can bring the output voltage into a steady state.
In an attempt to solve these problems the prior art created something called a soft start voltage ramp shown in FIG. 1 in the voltage reference circuit 42 as the soft start voltage reference signal 46. A soft start voltage reference 46 provides a reference voltage at start up or initialization of 0 volts and over a short period of time the voltage reference 46 ramps up to a steady state voltage reference, which continues to be used by the feedback circuitry of the buck converter to keep the output voltage at VOUT 12 of the buck converter at a steady output voltage. In other words, the soft start voltage reference signal starts at 0 volts and then ramps up to a steady state voltage as shown by the soft start voltage reference 46 in FIG. 1. In this prior art solution, if the output voltage at VOUT 12 is initially 0 volts then the soft start signal 46 works very well because there is a very small difference between the voltage feedback signal 34 and the voltage reference signal 40 at the input of the error amplifier 32. The error amplifier will output a voltage error signal 48, which will make the pulse width modulator produce a DH or modulation signal 20 with a duty cycle that will more likely than not produce voltage output at VOUT 12 that will usually not be too high for the circuitry powered by the buck converter. Here the error amplifier 32 will slowly increase and settle the signal to an appropriate output voltage using the soft start voltage signal 46 in conjunction with the voltage feedback signal 34. In essence, the voltage output voltage, more often than not, will rise with the voltage reference signal 46 in a controlled manner when the output voltage at VOUT 12 is initialized with a 0 volt bias at start up.
Conversely, the soft start voltage reference technique does not work when the output voltage at VOUT is at an intermediate voltage and the buck converter circuit is initialized. In other words, this prior art technique of using the soft start voltage reference 46 does not work very well when the output voltage at VOUT 12 is biased to a voltage that is between 0 volts and the desired output voltage of the buck converter. This condition is sometimes termed as a pre-biased voltage output condition. For example, if a soft start ramp is used and the prior art buck converter is initialized when the output voltage at VOUT 12 is in a pre-biased state, then the voltage feedback signal 34 and the voltage reference signal 40 will have a large error due to the soft start ramp voltage signal starting at 0 volts and the voltage feedback signal being greater than the initial start ramp voltage. Thus, the pulse width modulator 18 receives a signal from the error amplifier trying to reduce or increase or correct the duty cycle of the DH signal 20 causing the same problems as discussed above when a steady state voltage reference signal 44 was utilized. Here the pulse width modulator in conjunction with the error amplifier will be attempting to drive the output voltage at VOUT 12 down to 0 volts to match the soft start voltage reference signal 44 even though the voltage output is already biased at a non-zero voltage.